The hardware-in-the loop (HIL) testbed is developed to evaluate performance of the synchrophasor system components such as PMUs, and PDCs, and to measure the impact of the various errors on the synchrophasor based applications. Developed infrastructure allows performance evaluation of PMU estimation algorithms under scenarios defined in the relevant IEEE standards, as well as when exposed to real power grid operating conditions (e.g. faults on transmission line), and quantifying the impact of measurement errors on the application of interest.
The HIL testbed is implemented using the real-time simulator (OPAL-RT) and other commercial products (GPS receivers, industrial grade power amplifiers, PDCs) and it can be used for conducting the Application Tests as well as System End-to-End Tests. Network models and test scenarios are implemented on a real time platform. RT simulator is equipped with an I/O FPGA module used to provide inputs to device under test, and result measurements are send back to the simulator for further analyses and error quantification.